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SOC Physical Design Engineer Lead
SOC Physical Design Engineer Lead-March 2024
Bengaluru
Mar 30, 2025
ABOUT INTEL
Intel creates world-changing technology that enriches the lives of every person on earth.
10,000+ employees
Technology
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About SOC Physical Design Engineer Lead

  Job Description

  The Client Development Group is looking for a highly motivated Physical Design Lead to join the backend design team for the next generation of Client SOC. In this position, you will be responsible for managing and working on all aspects of physical design activities of Intel's SoCs in lower technology nodes. Direct Responsibilities: Physical design, convergence and signoff of blocks, sub-chip and SoCs. Responsibilities could include logic synthesis, floor planning, block and/or top level clocking, place and route. Own or work with full chip and block static timing engineers to close timing, formal verification, low power signoff and layout convergence. The ideal candidate will be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams/customers is expected. Ability to mentor other engineers and technically guide them. Experience with silicon which include processor cores and custom logic working together. Strong problem solving skills Strong written and verbal communication skills Capable of working in a high performing team to deliver the results required from the organization. Facilitator of direct and open communication, diversity of opinion, and debate

  Qualifications

  Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 8+ years' of experienceKey skills:Experience in all aspects of physical design flow in SOC.Experience in timing signoff, formal verification and low power static signoffExperience in all aspects of clock distribution.Experience in deep submicron process technology nodes is strongly preferredSolid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

  Other Locations

  IN, Hyderabad

  Posting Statement

  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

  Benefits

  We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

  It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

  Working Model

  This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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