Minimum qualifications:

　　Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

　　4 years of experience in physical design in the industry.

　　Experience in ECO (Engineering Change Order) flows for sign-off timing convergence.

　　Experience with PD (Physical Design) tools like Innovus and Fusion Compiler.

　　Experience with STA (Static Timing Analysis) tools like primetime or tempus.

　　Preferred qualifications:

　　Experience in the delivery of high performance silicon in latest technology process nodes.

　　Experience in extraction of design parameters, QoR metrics and analyzing data trends.

　　Experience and understanding in engineering across timing analysis, physical design and high level implementation.

　　Experience in overall Physical Design and Full-chip Timing closure with latest technologies.

　　Knowledge of semiconductor device physics and transistor characteristics.

　　Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

　　With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

　　Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

　　Drive the sign-off timing convergence for high performance designs at Full-chip and building block level.

　　Define the overall STA methodology, STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.

　　Implement complex block to meet high Performance, Power, Area (PPA) targets along with mentoring and developing other engineers in the team as a technical lead.

　　Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.