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Senior CPU/RTL Solutions Engineer
Senior CPU/RTL Solutions Engineer-March 2024
Austin
Mar 23, 2025
ABOUT CADENCE
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy t
5,001 - 10,000 employees
Technology
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About Senior CPU/RTL Solutions Engineer

  At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  Cadence Solutions team is looking for an Entry ( to 3 years experience) Level RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero markets. Position presents a learning and growth opportunity for candidate to develop into an architect (System) in the future.

  Responsibilities:

  CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP

  Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe, Ethernet, USB and other)

  Digital design and IP creation/ownership from High Level Arch Specification

  Create detailed Micro-architecture specification, work closely with the architect

  Understanding of performance measurement and refinement. Ability to work with verification/validation team to create performance verification plan

  RTL development

  Support Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug support

  Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correct

  Plan development schedule in detail and track deliverables to ensure timely IP delivery to all consumers

  Work with multi-disciplinary teams to ensure design block/IP success for all target specifications in Silicon

  Qualifications:

  BS/MS Engineering or Computer Sciences with 2+ years of Front End design

  Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

  Expert in RTL design (Verilog), simulators debuggers

  Experience in C/C++ and/or Python (or scripting language)

  Experience in Synthesis, LEC and CDC/RDC tools preferred

  Experience in driving results in multi-disciplinary organization

  Desirable:

  A Self-motivated person with good communication and design management skills

  Experience with Cadence front end toolset is a plus for this Job

  #LI-MA1

  We're doing work that matters. Help us solve what others can't.

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