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Senior ASIC Design Verification Engineer (Hardware)
Senior ASIC Design Verification Engineer (Hardware)-March 2024
Santa Clara
Mar 16, 2025
ABOUT PALO ALTO NETWORKS
Palo Alto Networks provides robust, innovative protection against cyberattacks.
10,000+ employees
Technology
VIEW COMPANY PROFILE >>
About Senior ASIC Design Verification Engineer (Hardware)

  Our Mission

  At Palo Alto Networks® everything starts and ends with our mission:

  Being the cybersecurity partner of choice, protecting our digital way of life.

  Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.

  Our Approach to Work

  We lead with flexibility and choice in all of our people programs. We have disrupted the traditional view that all employees have the same needs and wants. We offer personalization and offer our employees the opportunity to choose what works best for them as often as possible - from your wellbeing support to your growth and development, and beyond!

  At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work from the office three days per week, leaving two days for choice and flexibility to work where you feel most effective. This setup fosters casual conversations, problem-solving, and trusted relationships. While details may evolve, our goal is to create an environment where innovation thrives, with office-based teams coming together three days a week to collaborate and thrive, together!

  Your Career

  As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

  We expect office-based employees to be in the office three days per week, with two days working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive. Like so many companies, we are working through the details and things could change …. but in general if a role is deemed office-based we want our teams to be together four days per week.

  Your Impact

  Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification

  Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies

  Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers

  Define new tools and methodologies to continuously improve quality and velocity

  Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification

  Your Experience

  BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred

  Minimum 5 years experience in ASIC design verification

  Demonstrated success in taking multiple ASIC products from concept to mass production

  Expertise in SystemVerilog and UVM

  Technical strength in the following areas is required

  Defining test plans, including comprehensive adversarial testing

  Developing rich functional coverage models

  Creating powerful and scalable test benches

  Implementing sophisticated self-checking infrastructure with reference models and scoreboards

  Developing reusable constrained-random tests

  Debugging failures

  Closing coverage

  Experience in the following areas is preferred

  Networking and cyber security

  Formal property verification

  Silicon validation - bringup, test, debug, and regression

  Creating models in Python and C/C++ Writing driver code in C

  Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing

  Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status

  Strong leadership, collaboration, and communication skills

  The Team

  We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices.

  Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers’ existing investment in data, sensors, and enforcement points.

  Our Commitment

  We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

  We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected] .

  Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

  All your information will be kept confidential according to EEO guidelines.

  The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $200,600/yr to $324,500/yr. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here .

  Is role eligible for Immigration Sponsorship?: Yes

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