We are looking for a Principal Fullchip STA Engineer . As member of our DPU silicon team, your expertise in fullchip STA, timing ECOs, and timing quality are critical to our mission.
Responsibilities
Develop block & fullchip STA constraints; take ownership of critical IP interface constraints, verify correct implementation/integration and use of exceptions
Verify constraints quality and completeness
Build and update fullchip timing models for all design phases (early, intermediate, final signoff); generate timing reports & drive feedback to block owners to accelerate convergence
Analyze critical interfaces and ensure blocks have proper budgets for convergence
Drive ECO process for signoff
Qualifications
Required qualifications:
Bachelor’s degree in computer engineering, electrical engineering, or related field
10+ years of physical design experience, with focus on STA at cluster or fullchip levels, and a track record of successful tapeouts in advanced process nodes
Strong experience with Synopsys PrimeTime for analysis and DMSA ECO flows
Strong understanding of timing constraints (exceptions, budgeting, CDC issues, clocking constraints)
Strong scripting skills in Perl or TCL
Preferred qualifications:
15 years of physical design experience, with focus on STA at cluster or fullchip levels, and a track record of successful tapeouts in advanced process nodes
Experience with PrimeClosure/PrimeECO flows
Experience with flow automation for timing/budgeting flows
Strong scripting skills in Perl or TCL
Strong understanding of timing constraints (exceptions, budgeting, CDC issues, clocking constraints)
Strong understanding of derating & margining methodologies
Tapeout experience in TSMC 7nm or below, or comparable
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