Job Description
We are working on the next generation RTL-to-GDSII solution. You will be working primarily on C++ and should be able to completely own and drive the design and development of various pieces of the RTL synthesis technology, logic optimizations and power synthesis.
Must Requirements:
2-7 years of experience in software developmentB.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college.Good knowledge of C/C++, algorithm and data structuresGood problem solving and analytical skillsShould be able to guide and lead others, towards project completion.
Good to have experience or understanding in:
RTL synthesis tool development.System Verilog, VHDL, UPF, DFT, formal verification, Dynamic Power.RTL & gate level logic optimizationsParallel algorithms & jobs distributionScripting languages (Python, Tcl, Perl)