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　　FAST SOCDV AE Job Description Document

　　Job Title: Lead Solution Engineer - FE

　　Location: Bangalore

　　Send profile to kmadhup@cadence.com

　　Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

　　The Cadence Advantage

　　The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.The unique "One Cadence - One Team" culture builds and fosters diversity, equity and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interestsYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

　　Job Summary

　　As a member of the FAST Organization for the Front-End Verification team, you will partner with world-wide Cadence customers to provide front end verification services from RTLDV to Post Silicon Validation. This involves working closely with the customers to understand their Product requirements, involving in System Architecture discussions and defining the DV methodologies to fulfill their requirements. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest DV practices in industry and demonstrate expertise by authoring high impact knowledge content.

　　This role also provides opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with Design teams to identify and prioritize the product improvement initiatives with your timely feedback and observations.

　　This an excellent opportunity to work in a supportive, flexible and friendly work environment that FAST Solution team offers, where we are vested in each other's success, and are passionate about technology and innovation.

　　Job Responsibilities

　　Become a PoC for assigned module and deliver high quality TB and Testcases to Cadence customersProvides a proactive and creative approach to resolving problems using specialized domain knowledgeGuides creation and publishing of high quality and impactful knowledge content in SOCDV/IPDV as per Customer RequirementsProvides effective technical leadership and mentoring for a small team working at Cadence to deliver quality results according to schedule requirementsSolves highly complex problems and is able to identify viable and often innovative options, and uses analytical skills and judgment to recommend an appropriate solutionQualifications

　　Bachelor's Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 4 years related experienceOR Masters 4 years of related experienceOR PhD 3 years of related experience

　　Experience and Technical Skills required

　　> 4 years of experience in Processor based full chip verification / IP VerificationKnowledge of Verilog/System Verilog, digital simulation and debugKnowledge of HS/LS Protocols / Processor based SOC architecture and digital design fundamentalsSkilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology / formal / Power Aware Simulations / GLSExperience with C/C++. Debugging disassembly assembly is a plusExperience with RTL to Post Silicon Validation DV methodologies/flows is a plusExperience with perl, python or similar scripting language is a plusExpert level experience with multiple industry standard tools usage (preferably Cadence tools),Ability to analyze customer's environment and evaluate appropriate solutions; able to architect flows; anticipates technical issues and develops creative solutions before they become a problemAbility to work independently, must have excellent debugging skills and ability to separate out the critical issues from trivial ones.

　　Behavioral skills required

　　Must possess strong written, verbal and presentation skillsAbility to establish a close working relationship with both customer peers and managementExplore what's possible to get the job done, including creative use of unconventional solutionsWork effectively across functions and geographiesPush to raise the bar while always operating with integrity

　　Regards

　　K Madhu Prasad (Madhu Reddy)

　　kmadhup@cadence.com

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