Minimum qualifications:

　　Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.

　　10 years of experience in various areas of SoC physical design working with physical design flows and methodologies (e.g., synthesis, STA, formal verification, CDC, power analysis).

　　5 years of experience managing SoC development teams.

　　Preferred qualifications: Experience in solving physical design issues across various technologies such as embedded processors, DDR, networking fabrics.

　　Experience in IP integration (e.g., memories, IO's and Analog IP).

　　Experience with ASIC or COT models.

　　Knowledge of chip design and implementation topics (e.g., digital design, design verification, physical design, EDA, power, synthesis).

　　Knowledge of Verilog/System Verilog.

　　Excellent communications skills, with the ability to influence others.

　　About the job

　　Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

　　Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

　　In this role, you will help deliver products that have a substantive impact on the technical infrastructure that powers Google. You will provide leadership to a group of Silicon engineers in an innovative and fast-paced environment with a focus on physical implementation. You will own and drive technical projects from the concept/planning stage through execution and closure. You will bring out the best in the team to deliver designs that work the first time in a number of different application areas.

　　Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

　　The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

　　Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

　　Responsibilities

　　Lead a team of physical design engineers to develop physical design methodologies, tools and automation scripts for various implementation steps.

　　Create execution plans including vendor engagements, technical evaluations, process nodes and IP.

　　Collaborate with teams across Google to identify and create opportunities for custom silicon innovation.

　　Understand architecture and design specifications with the team, and define physical design strategies and tactics to meet quality and schedule goals.

　　Work closely with architecture, design and implementation stakeholders to provide status and iterative milestones.