Home
/
Comprehensive
/
DFX Design Engineer
DFX Design Engineer-July 2024
Folsom
Jul 8, 2025
ABOUT INTEL
Intel creates world-changing technology that enriches the lives of every person on earth.
10,000+ employees
Technology
VIEW COMPANY PROFILE >>
About DFX Design Engineer

  Job Description

  Do Something Wonderful!

  The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!

  Who We Are

  The Memory IP Group (MIP) within the Client Engineering Group (CEG) is looking for a DFX Design Engineer to work on DDR/LPDDR Hard IP's. In this role you will work with an experienced Mixed Signal design team to develop scan/dfx solutions for DDR/LPDDR PHY designs going into CPU and Networking products. You will be responsible for taking the design from product definition through design, synthesis, hardening, post-silicon enabling and High-Volume Manufacturing (HVM).

  Who You Are

  Responsibilities of the role include, but not limited to:

  Contributing to specifications at multiple levels, including the HAS (High Level Architecture Spec) and MAS (Micro-Architecture Spec)

  Work with multiple disciplines (Logic, Validation, Circuits, Structural Desing, and HVM) to define and debug DFX solutions to meet IP and SOC needs.

  Implement RTL/System Verilog and analyze quality (Lint, CDC etc).

  Setup, debug, and support Spyglass DFT

  Define and debug scan insertion scripts for synthesis.

  Analyze and improve scan coverage.

  Work with Structural Design team to synthesize and close timings for DFX features.

  Enabled and debug Scan/DFX content in Post-Silicon for High Volume Manufacturing (HVM)

  Qualifications

  Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

  Minimum Qualifications :

  Possess a Bachelor's Degree in Electrical/Computer Engineering with 3+ years of industry experience OR a Master's Degree in Electrical/Computer Engineering with 2+ years of industry experience.

  Experience should be concentrated in the following areas:

  RTL coding experience including logic and behavioral modelling.

  Experience with one or more of the following tools (eg. Tessent ATPG, Spyglass DFT, VCS, and Fusion Compiler)

  Experience debugging various simulation failures.

  Experience with Structural design flows including Synthesis, Floor planning, and Speed path analysis.

  Experience with debugging and enabling Post-Silicon content for High Volume Manufacturing

  Preferred Qualifications:

  Understanding of High Speed IO Mixed Signal Design

  Hard IP DFX design, verification, and SOC Integration experience.

  Experience with High Volume Manufacturing requirements and Test development

  Familiarity with standard industry DFX IP features (TAP, Boundary Scan, mbist, Scan etc.)

  Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

  Other Locations

  US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara

  Posting Statement

  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

  Benefits

  We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

  Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00

  *Salary range dependent on a number of factors including location and experience

  Working Model

  This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Comments
Welcome to zdrecruit comments! Please keep conversations courteous and on-topic. To fosterproductive and respectful conversations, you may see comments from our Community Managers.
Sign up to post
Sort by
Show More Comments
SIMILAR JOBS
Advanced Lead Engineer - Emerging Technologies
Job Description Summary This is an Advanced Lead Engineer position in Mechanical Systems Engg team. Activities aimed at proving a concept to be valid or technically feasible by the application of sci
Pharmacy Technician
Bring your heart to CVS Health. Every one of us at CVS Health shares a single, clear purpose: Bringing our heart to every moment of your health. This purpose guides our commitment to deliver enhanced
APRENDIZ
Acerca de Abbott Abbott es líder mundial en cuidado de la salud, creando ciencia innovadora para mejorar la salud de las personas. Siempre estamos mirando hacia el futuro, anticipando cambios en la c
Part-Time Beauty Advisor - Sephora
Drive sales through an authentic passion for beauty. Engaging Clients through identifying their needs with a consultative approach, top beauty brands and best in class merchandise sets. Key Accountab
Cloud Software Engineer 3
Date Posted: 2024-01-16 Country: United States of America Location: MD233: 420 National Business Parkway 420 National Business Parkway Suite 400, Annapolis Junction, MD, 20701 USA Position Role Type:
Mgr-Loss Prevention
Job Number 24014404 Job Category Loss Prevention & Security Location Sheraton Tunis Hotel, Avenue de la Ligue Arabe, Tunis, Tunisia, Tunisia Schedule Full-Time Located Remotely? N Relocation? N P
Senior Member Technical Staff (JoinOCI-SDE)
Job Description Design, develop, troubleshoot and debug software programs for databases, applications, tools, networks etc. Responsibilities At Oracle Cloud Infrastructure (OCI), we build the future
Technical Support Analyst - Cloud Payments (Columbia, MD OR Orlando, FL)
Job Description Technical Support Analyst - Cloud Payments to work out of our Columbia, MD OR Orlando, FL office : We are seeking a highly skilled and motivated Technical Support analyst to join our
Site Operations Coordinator
Overview American Nursing Care is a mission-driven organization that knows kindness and compassion makes the world a better place. Serving our communities, together, we can make the healing presence
Assistant Manager Reservation
Job Number 24014443 Job Category Reservations Location Courtyard Amritsar, 52 Mall Road, Amritsar, Punjab, India Schedule Full-Time Located Remotely? N Relocation? N Position Type Management JOB SUMM
Copyright 2023-2025 - www.zdrecruit.com All Rights Reserved