At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow's reality.

　　We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

　　Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

　　Job Responsibilities

　　Working on 3nm and 5nm designs with various customers for deployment of Aprisa place and route tools. Expertise in solving customer's problems for critical designs to achieve desired performance, area and power targets. Responsible to develop flow and methodology for doing placement, CTS and routing. Provide training and technical support to customers using Aprisa toolsHandle and grow team of engineers to work on critical customer and internal projects

　　Job Qualifications

　　Typically requires minimum of 15+ years of experience in Physical Design with mainstream P&R toolsShould be able to manage team of junior product engineers and lead successful customer engagements.Should be able to understand and communicate with customers and internal teams on the exact issues and requirements.Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.Hands-on experience with commercial place & route tools like Synopsys-ICC2/FC, Cadence-lnnovus or Aprisa is a must. Tapeout experience of 2 or more projects is a must. Good understanding of timing, power and area trade-offs. Experience delivering designs with multiple voltage islands and top-level floorplanning & chip-assembly is a plus.TCL, Perl or Python scripting is a plus.Strong verbal and written communication skills; good presentation skillsGood problem solving and debugging skillsProficiency in Korean and English is requiredBachelors in Electronics and Communication (E&C) or Electrical or Telecom EngineeringMasters in VLSI or Microelectronics is a plus

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