At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

　　The Cadence Advantage

　　The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

　　Job responsibilities:

　　We are looking for a motivated R&D engineer to help develop Cadence's Verification Acceleration and Co-Emulation environment. The engineer will be a part of cross geography team in developing maintainable, high-quality C/C++ code for a HDL language based compiler and runtime support. Responsibilities include development of HDL compiler front-end for SV, VHDL LRM support, improving compiler performance and infrastructure. Exposure to RTL simulation/synthesis and runtime environment is highly desirable.

　　Position Requirements

　　• BS / MS in Computer Science or equivalent required.

　　• At least 5 years of software and product development experience.

　　• Proficient in C/C++ SW development using advanced data-structures and algorithms and heuristics along with excellent and debugging skill

　　• Prior experience and understanding of EDA front-end tools and compiler concepts like parsing elaboration of HDL is desirable.

　　• Experience or understanding of System Verilog or VHDL language constructs and RTL Simulation concepts with be preferred

　　• Hardware knowledge and background in RTL design and/or verification is highly desirable.

　　• Additional knowledge of shell or Perl or TCL scripting, python, and functional programming will be preferred.

　　• Good problem-solving abilities and excellent writing and communication skills.

　　• Keywords - Data Structures, Algorithms, C/C++, Data Structures, System Verilog, VHDL, RTL, Simulation, Compilers, UVM, TLM, RTL modeling, emulation.

　　We're doing work that matters. Help us solve what others can't.