At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM, NAND Flash, eMMC, DFI PHY, and UFS models for use on hardware based verification products.

　　Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.

　　Perform as individual and collaborative contributor for RTL design, verification, productizing, and documentation of memory IP.

　　Requires a collaborative temperament, articulate and proactive expression of ideas, and good communication skills with diverse behavioral styles.

　　Interface with internal and external customers to work on diverse problems and solutions related to use of memory model IP in emulation or verification.

　　As a team member and collaborator working with folks in a fast-moving industry, this role requires flexibility, adaptability, curiosity, energy, and stability with an open listening heart and a "YES" brain.

　　Team member will develop and use lifecycle processes to ensure product quality.

　　Essential:

　　The position requires MSEE or equivalent with a minimum of 3 years of related experience in designing hardware systems OR BSEE or equivalent with a minimum of 5 yrs of industry experience in designing hardware systems.

　　MUST have advanced fluency and communication skills with both written and spoken technical and casual English.

　　RTL design knowledge using Verilog/SystemVerilog is required

　　Experience in protocol-based development

　　Hands-on experience using RTL verification tools and flows

　　Demonstrable debugging experience is critical

　　Familiar with team-wide collaboration tools and process

　　Drive and ability to schedule workload and plan own tasks effectively

　　Strongly recommended:

　　Verification experience using Cadence simulation and/or emulation products

　　Programming experience with scripting languages like Perl, TCL, C-shell

　　Knowledge of memory sub-system design and operation

　　If you are excited by the opportunity and challenge of bringing this hard-to-find set of qualities and behaviors to our MMP product engineering role, you'll relish becoming a true expert problem solver in the memory protocol domain, a true expert in verification use models within the Palladium and Protium products, and a true expert in navigating and building business oriented customer relationships.

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